Port H Data Direction Register; Table 21-33. Phddr Register; Table 21-34. Phddr Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

21.2.3.16 Port H Data Direction Register

PHDDR is the Port H Data Direction Register. The active bits used in this register are
Read/Write. Bits set in PHDDR set the corresponding PH pin to be an output:
• Bit [7] controls pin 125 when the pin is configured as PH7. It does not control pin 125
when the pin is configured as LCDDCLK.
• Bit [6] controls pin 128 when the pin is configured as PH6. It does not control pin 128
when the pin is configured as LCDLP or LCDHRLP.
• Bit [5] controls pin 129 when the pin is configured as PH5. It does not control pin 129
when the pin is configured as LCDFP or LCDSPS.
• Bit [4] controls pin 130 when the pin is configured as PH4. It does not control pin 130
when the pin is configured as LCDEN or LCDEN.
• Bit [3] controls pin 131 when the pin is configured as PH3. It does not control pin 131
when the pin is configured as LCDVD11.
• Bit [2] controls pin 132 when the pin is configured as PH2. It does not control pin 132
when the pin is configured as LCDVD10.
• Bit [1] controls pin 133 when the pin is configured as PH1. It does not control pin 133
when the pin is configured as LCDVD9.
• Bit [0] controls pin 135 when the pin is configured as PH0. It does not control pin 135
when the pin is configured as LCDVD8.
Clearing a bit configures the pin to be an input. A System Reset clears all bits.
NOTES:
1. The LCDHRLP function applies to the LH75401 and LH75411 SoC devices only.
2. The LH75400 and LH75410 SoC devices support a single LCDEN function on pin 130.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0

Table 21-33. PHDDR Register

31 30 29 28 27
0 0 0 0
R R R R
15 14 13 12 11
///
0 0 0 0
R R R R

Table 21-34. PHDDR Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Port H Output/Input
Port H Data Direction
Bits set = Port H output.
Bits cleared = Port H input.
26 25 24 23
///
0 0 0 0 0
R R R R R
10 9 8 7
0 0 0 0 0
R R R R RW
0xFFFDC000 + 0x0C
6/17/03
General Purpose Input/Output
22 21 20 19
0 0 0 0
R R R R
6 5 4 3
Port H Data Direction
0 0 0 0
RW RW RW RW RW
FUNCTION
18 17 16
0 0 0
R R R
2 1 0
0 0 0
RW RW
21-19