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LH75400/01/10/11 (Preliminary) User's Guide
19.3.2 UART0 and UART1 Interrupts
Both UART0 and UART1 have a combined interrupt. Only UART1 has separate
UARTRXINTR and UARTTXINTR. The individual UART interrupt outputs are OR'd
together to produce the combined interrupt for UART0 and UART1. However, UART1 has
separate UARTRXINTR and UARTTXINTR interrupts. The individual UART interrupt out-
puts are OR'd together to produce the combined interrupt for that UART. Interrupt condi-
tions within the combined interrupt are individually maskable.
The combined interrupt for UART1 has UARTRXINTR and UARTTXINTR, even though
they are connected to the VIC. If using all three interrupts, exercise care when assigning
the priorities in the VIC.
19.3.2.1 UARTRXINTR
UARTRXINTR is the receive interrupt. This interrupt changes state when one of the FIFO
events in Table 19-32 occurs:
FIFOs are enabled and the receive FIFO
reaches the programmed trigger level.
FIFOs are disabled (have a depth of one
location) and data is received, filling
the location.
19.3.2.2 UARTTXINTR
UARTTXINTR is the transmit interrupt. The transmit interrupt is based on a transition
through a level, rather than on the level itself. When the interrupt and the UART are enabled
before any data writes to the transmit FIFO, the interrupt is not set. The interrupt is only set
after written data exits the single location of the transmit FIFO, leaving the FIFO empty.
FIFOs are enabled and the transmit FIFO
reaches the programmed trigger level.
FIFOs are disabled (have a depth of one
location) and no data is present in the
transmitter's single location.
19.3.2.3 UARTINTR
The UARTINTR interrupt is the combined interrupt for UART0 and UART1. It is asserted
if one or more of the other interrupts are asserted.
Table 19-32. UARTRXINTR State
FIFO EVENT
Table 19-33. UARTTXINTR State
FIFO EVENT
7/15/03
RECEIVE INTERRUPT STATUS
Receive interrupt is cleared by either:
• Reading data from the receive FIFO until it becomes less than
the trigger level, or
• Clearing the interrupt.
Receive interrupt is cleared by either:
• Performing a single read of the receive FIFO, or
• Clearing the interrupt.
TRANSMIT INTERRUPT STATUS
The transmit interrupt is cleared by either:
• Writing data to the transmit FIFO until it becomes greater than
the trigger level, or
• Clearing the interrupt.
The transmit interrupt is cleared by either:
• Performing a single write to the transmit FIFO, or
• Clearing the interrupt.
UART0 and UART1
19-25
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