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UART0 and UART1
19.3.1.11 Interrupt FIFO Level Select Register
IFLS is the Interrupt FIFO Level Select Register. The active bits used in this register are
Read/Write.
The IFLS Register defines the FIFO level at which interrupts are generated to request ser-
vice for the receive and transmit FIFOs. The interrupts are generated based on a transition
through a level rather than being based on the level. That is, the design is such that the
interrupts are generated when the fill level progresses through the trigger level. The bits
are reset so that the trigger level is when the FIFOs are at the half-way mark.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
19-18
Table 19-21. IFLS Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
0
0
0
0
0
R
R
R
R
R
Table 19-22. IFLS Register Definitions
BIT
NAME
31:6
///
RECEIVE
5:3
INTERRUPT FIFO
LEVEL SELECT
TRANSMIT
2:0
INTERRUPT FIFO
LEVEL SELECT
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
///
0
0
0
0
R
R
R
R
10
9
8
7
///
0
0
0
0
R
R
R
R
UART0: 0xFFFC0000 + 0x034
UART1: 0xFFFC1000 + 0x034
DESCRIPTION
Reserved Do not modify.
Trigger Points for the Receive Interrupt
000 = Receive FIFO becomes
001 = Receive FIFO becomes
010 = Receive FIFO becomes
011 = Receive FIFO becomes
100 = Receive FIFO becomes
101:111 = Reserved.
Trigger Points for the Transmit Interrupt
000 = Transmit FIFO becomes
001 = Transmit FIFO becomes
010 = Transmit FIFO becomes
011 = Transmit FIFO becomes
100 = Transmit FIFO becomes
101:111 = Reserved.
7/15/03
22
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
0
0
1
0
0
R
RW
RW
RW
RW
≥
1/8 full.
≥
1/4 full.
≥
1/2 full.
≥
3/4 full.
≥
7/8 full.
≤
1/8 full.
≤
1/4 full.
≤
1/2 full.
≤
3/4 full.
≤
7/8 full.
17
16
0
0
R
R
1
0
1
0
RW
RW
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