Timer Control Register; Table 20-35. Tmctrl Register; Table 20-36. Tmctrl Register Definitions - Sharp Blue Treak LH75400 User Manual

UART2

20.3.2.13 Timer Control Register

Register Bank: 1
TMCTRL is the Timer Control Register. The active bits used in this register are Write Only.
The TMCTRL Register controls the operation of the following UART timers:
• STA and TGA
• STB and TGB.
A timer has no effect when it is configured as a baud-rate generator. TGA and TGB are not
reset after command execution.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
NOTE: The reset value of this register's bits is indeterminate.
BITS
31:6
5
4
3:2
1
0
20-24

Table 20-35. TMCTRL Register

31 30 29 28 27
0 0 0 0 0
— — — — —
15 14 13 12 11
0 0 0 0 0
— — — — —

Table 20-36. TMCTRL Register Definitions

NAME
/// Reserved Do not modify.
Timer-B Gate Serves as a gate for Timer B operation.
TGB
0 = Disables counting.
1 = Enables counting.
Timer-A Gate Serves as a gate for Timer A operation.
TGA
0 = Disables counting.
1 = Enables counting.
/// Reserved Read as zero.
Start Timer B Loads/reloads Timer B with its count value (BBH/BBL).
STB
At terminal count a status bit is set in TMST (TBEx).
Start Timer A Loads/reloads Timer A with its count value (BAH/BAL).
STA
At terminal count, a status bit is set in TMST (TAEx).
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23
///
0 0 0 0
— — — —
10 9 8 7
///
0 0 0 0
— — — —
0xFFFC2000 + 0x0C
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
— — — — —
6 5 4 3 2
TGB TGA ///
0 1 1 0 0
— — — — —
17 16
0 0
— —
1 0
STB STA
0 0
— —