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LH75400/01/10/11 (Preliminary) User's Guide
20.2.1 UART Receiver Data Frame
A UART receiver data frame has the following structure:
• A start bit that indicates the beginning of the frame. The start bit consists of a '0' on the
receiver input for one bit period.
• Data, which consists of at least five and no more than nine data bits
• An optional parity bit, which can be used with available hardware for parity error checking
• One or more stop bits, which indicate the end of the frame. Stop bits consist of a '1' on
the receiver input for as many bit periods as the number of stop bits previously specified
when programming the receiver.
The UART receiver is in the marking state (i.e., the input is 1) from the time when a stop bit
is sent until the time the next start bit is received. When the receiver receives an entire
frame, the UART transfers the received data and the frame status to the receiver FIFO. This
buffer can have a depth of either four words (FIFO Mode) or one word (Character Mode).
The UART receiver:
• Synchronizes the incoming data
• Passes it through a digital filter to filter out the spikes
• Samples the UART2RX pin either three or seven times at a frequency of 16X the bit rate
to generate the data bit. The number of sampling times is programmable.
Bit-polarity decisions are made by majority voting. If all samples do not agree, the bit is
reported as a noisy bit in the RXF Register. To compensate for such environments, the
3/16 Sampling Mode can be used for high-frequency transmissions or when serious resis-
tance-capacitance (RC) delays are expected on the channel. Similarly, the 7/16 Sampling
Mode can be used for noisy media.
The UART receiver also uses a Digital Phase Lock Loop (DPLL) to overcome frequency-
shift problems. However, using the DPLL in a very noisy environment can increase errors.
For this reason, the DPLL can be disabled with the RMD Register.
6/17/03
UART2
20-3
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