Ssp Registers; Uart0 And Uart1 Registers; Chapter 26 - Register Map; Table 26-15. Ssp Register Summary - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary

Table of Contents

LH75400/01/10/11 (Preliminary) User's Guide

26.13 SSP Registers

Base address: 0xFFFC6000

UART0 Base Address: 0xFFFC0000

UART1 Base Address: 0xFFFC1000

0x01C - 0xFFF

All other address locations are reserved and must not be used during normal operation.

0x008 - 0x014

0x01C - 0x020

0x04C - 0x07C

0x080 - 0x08C

0x090 - 0xFFC

0x0000 Control Register 0

0x0000 Control Register 1

0x0000 Receive FIFO (Read)/Transmit FIFO (Write)

Status Register

Clock Prescale Register

Interrupt Identification Register (read)/Interrupt

Clear Register (write)

Receive Timeout Register

Data read or written from the interface. It is 12 bits wide

on a read and 8 on a write.

Receive Status Register (read)/Error Clear Register (write)

0x00000090 Flag Register (read only)

Integer Baud Rate Divisor Register

Fractional Baud Rate Divisor Register

Line Control Register, HIGH byte

UART Control Register

Interrupt FIFO Level Select Register

Interrupt Mask Set/Clear Register

Raw Interrupt Status Register

Masked Interrupt Status Register

Interrupt Clear Register

DMA Control Register