General Enable Register; Table 20-13. Ger Register; Table 20-14. Ger Register Definitions - Sharp Blue Treak LH75400 User Manual

UART2

20.3.2.5 General Enable Register

Register Bank: 0
GER is the General Enable Register. The GER Register enables or disables the bits of the
GSR Register from being reflected in the GIR Register. GER acts as the Device Enable
Register, masking the interrupt requests from the UART blocks.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
20-14

Table 20-13. GER Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R

Table 20-14. GER Register Definitions

BITS NAME
31:6 ///
5 TIE
4 TxIE
3 ///
2 RxIE
1 TFIE
0 RFIE
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
///
0 0 0 0
R R R R
0xFFFC2000 + 0x04
DESCRIPTION
Reserved Do not modify. Read as zero.
Timers Interrupt Enable
Transmitter Interrupt Enable
Reserved Read as zero.
Receiver Interrupt Enable
Transmit FIFO Interrupt Enable
Receive FIFO Interrupt Enable
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
TIE TxIE ///
0 0 0 0 0
R RW RW R RW
17 16
0 0
R R
1 0
0 0
RW RW