LH75400/01/10/11 (Preliminary) User's Guide
2.6 LH75401 Signal Descriptions
PIN NO. SIGNAL NAME
1
2
4
5
6
7
9
10
D[15:0]
12
13
15
16
18
19
20
21
22
nWE
23
nOE
24
nWAIT
25
nBLE1
27
nBLE0
28
nCS3
29
nCS2
30
nCS1
31
nCS0
32
33
35
36
37
38
39
40
43
44
45
46
A[23:0]
47
49
50
51
52
53
55
56
57
58
60
61
72
DREQ
73
DACK
Table 2-2. LH75401 Signal Descriptions
TYPE
MEMORY INTERFACE (MI)
Input/Output Data Input/Output Signals
Output
Static Memory Controller Write Enable
Output
Static Memory Controller Output Enable
Input
Static Memory Controller External Wait Control
Output
Static Memory Controller Byte Lane Strobe
Output
Static Memory Controller Byte Lane Strobe
Output
Static Memory Controller Chip Select
Output
Static Memory Controller Chip Select
Output
Static Memory Controller Chip Select
Output
Static Memory Controller Chip Select
Output
Address Signals
DMA CONTROLLER (DMAC)
Input
DMA Request
Output
DMA Acknowledge
DESCRIPTION
7/15/03
LH75401 SoC
NOTES
1
2
2
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
2
1
1
1
2-9