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Chapter 10
Vectored Interrupt Controller
The Vectored Interrupt Controller (VIC) provides the principle user interface to the
interrupt system.
10.1 Theory of Operation
All internal and external interrupts are routed to the VIC, where interrupt priority is deter-
mined by hardware. The VIC is also where the appropriate signal to the processor (IRQ or
FIQ) is generated. The CPU services the interrupt as either a vectored interrupt or a
default-vectored interrupt.
The VIC uses a set of 32-bit registers to configure, control, and determine the status of the
VIC. These registers are described in Section 10.2.2.
On reset, the VIC is configured to pass all interrupts through to the CPU IRQ input as
default-vectored IRQ interrupts. In the reset configuration, the VIC Status Registers can
be used in a conventional way to service interrupts using the CPU IRQ Exception Vector
at address 0x18. Users must configure the VIC to use the vectored interrupt feature. The
VIC's software-generated interrupt feature is available immediately out of reset.
10.1.1 Interrupts
The VIC accepts inputs from 32 interrupt source lines:
• Seven of the interrupt source lines are external
• Twenty-three of the interrupt source lines are internal
• Two interrupt source lines that can be used as software interrupts.
All 32 interrupt source lines can be enabled, disabled, and cleared individually, and indi-
vidual status may be determined. On reset, all interrupts are disabled.
The VIC also accepts software-generated interrupts. A software-generated interrupt can be
invoked on any interrupt line to force a specific Interrupt Service Routine (ISR) to execute
in the absence of a hardware interrupt. This is useful for lines designated as 'spare;' how-
ever, a software interrupt can be generated on any of the 32 interrupt lines. A software-gen-
erated interrupt adheres to the same enabling control as hardware-generated interrupts.
The VIC provides 32 interrupts:
• 16 vectored interrupts
• 16 or more default-vectored interrupts.
A vectored interrupt results in a low-latency invocation of the service routine for that par-
ticular interrupt. A default-vectored interrupt requires the CPU to perform additional pro-
cessing to determine which interrupt source caused the interrupt.
6/17/03
10-1
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