Pins Pa7/D15 To Pa0/D8 Resistor Muxing Register; Table 11-16. Pa_Res_Mux Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

11.2.2.6 Pins PA7/D15 to PA0/D8 Resistor Muxing Register

PA_RES_MUX is the Pins PA7/D15 to PA0/D8 Resistor Muxing Register. This register
allows the pull-up/pull-down to be configured as needed. The active bits used in this reg-
ister are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:16
15:14
13:12
11:10
9:8
7:6
Table 11-15. PA_RES_MUX Register
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
PA7 PA6
1 0 1 0 1
RW RW RW RW RW

Table 11-16. PA_RES_MUX Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Pin PA7/D15 Resistor Source
00 = Pull-down
PA7
01 = Pull-up
10 = No pull-up or pull-down (default)
11 = Pull-up
Pin PA6/D14 Resistor Source
00 = Pull-down
PA6
01 = Pull-up
10 = No pull-up or pull-down (default)
11 = Pull-up
Pin PA5/D13 Resistor Source
00 = Pull-down
PA5
01 = Pull-up
10 = No pull-up or pull-down (default)
11 = Pull-up
Pin PA4/D12 Resistor Source
00 = Pull-down
PA4
01 = Pull-up
10 = No pull-up or pull-down (default)
11 = Pull-up
Pin PA3/D11 Resistor Source
00 = Pull-down
PA3
01 = Pull-up
10 = No pull-up or pull-down (default)
11 = Pull-up
26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
PA5 PA4 PA3
0 1 0 1
RW RW RW RW
0xFFFE5000 + 0x14
DESCRIPTION
6/17/03
I/O Configuration
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
PA2 PA1
0 1 0 1 0
RW RW RW RW RW
17 16
0 0
R R
1 0
PA0
1 0
RW RW
11-11