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LH75400/01/10/11 (Preliminary) User's Guide
The following steps summarize the DMA process:
1.
The external request signal (DREQ) starts a peripheral DMA transfer.
2.
The DMA Controller requests use of the AHB.
3.
When the AHB arbiter grants the AHB to the DMA Controller, the DMA Controller fills
its FIFO with the number of data units specified by the burst length (1, 4, 8, or 16).
4.
The DMA Controller continues to request the AHB following the completion of the
burst transfer. However, it may lose ownership of the AHB if a higher priority bus mas-
ter is also requesting the AHB.
5.
When the AHB arbiter re-grants the AHB to the DMA Controller, the FIFO is emptied
by writing the FIFO contents to the destination with data being of a width set by the
destination data width (byte, half-word or word). The filling and emptying of the FIFO
for a burst transfer is always completed for the current stream being serviced before
another stream DMA request is serviced.
6.
As DMA requests are received, the DMA Controller arbitrates between them, assign-
ing a requesting source to be serviced based on the priority indicated in Table 12-1.
A data packet transfers from the source to the DMA FIFO, then transfers from the
FIFO to the destination.
Exceptions to the DMA process are:
• When the DMA is configured to perform a memory-to-memory transfer followed by a
peripheral-to-memory transfer, the transfer starts immediately, without the DMA waiting
for the external request signal in step 1. The software workaround to this is:
– Set up a memory-to-memory access.
– Let the memory-to-memory complete.
– Set up the peripheral-to-memory transfer, but without the enable bit set.
– Perform a second write operation, with the enable bit set.
• When the DMA is configured to perform an external memory-to-peripheral write
operation. This operation may cause the processor to hang when:
– All DMA registers, except CTRL, have been initialized properly.
– A write to the Status Clear bits (bits [7:0]) in the CLR Register for Data Stream 2 has
been performed.
– The DMA Controller Enable bit (bit [2]) in the CTRL Register has been set.
To avoid this situation, use this procedure to start an external Memory-to-Peripheral
DMA transfer:
a. Set up the Stream 2 DMA Control Register for the transfer except have the enable
b.
c.
d. Set bit 0 of the temp variable.
e. Write the temp variable to the Stream 2 Control Register.
• When Stream3 is used for memory-to-memory transfers, the transfer starts when software
sets an enable bit in the Control Register for that stream. The transfer is conducted in
bursts, with the bursts executing back-to-back until the required number of data units are
transferred. The DMA Controller retains ownership of the AHB between successive bursts,
unless the AHB Arbiter de-grants the DMA Controller for a higher priority bus master.
bit clear.
Read the value of the current Stream 2 DMA Control Register into a temp variable.
Write the temp variable back to the current Stream 2 Control Register.
Direct Memory Access Controller
7/15/03
12-3
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