Reset Status Clear Register; Table 9-13. Resetstatusclr Register; Table 9-14. Resetstatusclr Register Definitions - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary

Table of Contents

LH75400/01/10/11 (Preliminary) User's Guide

9.3.2.6 Reset Status Clear Register

ResetStatusClr is the Reset Status Clear Register. This Write Only register clears the

Reset Status flags. When writing to this register, each HIGH data bit causes the corre-

sponding bit in the Reset Status Register to be cleared. LOW data bits have no effect on

their corresponding bit in the Reset Status register. Writing to undefined bits has no effect

on the RCPC.

NOTE: The reset value of this register's bits is indeterminate.

BITS FIELD NAME

Table 9-14. ResetStatusClr

Clear WDT Timeout

1 = Clears WDTO in the ResetStatus Register. Reads of this bit are

unpredictable.

Clear External Reset

1 = Clears EXT in the ResetStatus Register. Reads of this bit are

unpredictable.

Reset, Clock, and Power Controller

0xFFFE2000 + 0x14

Reads undefined. Write zero only.