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Static Memory Controller
BITS
15:11
10
9:5
4
3:0
7-20
Table 7-17. BCR3 Register Definitions (Cont'd)
NAME
Wait State2
For SRAM: WST2 is the write access time burst access time for burst ROM.
The wait state time is (WST2 + 1) × tHCLK.
WST2
For Burst ROM: WST2 is the burst access time. This wait state time is
(WST2) × tHCLK.
Note that tHCLK = system clock period. WaitState2 does not apply to on-burst
ROM devices. (Default = 11111)
Read Byte Lane Enable:2
0 = All byte lane strobes nBLE[1:0] are held HIGH during any system reads or
writes from memory (default at system reset).
1 = All byte lane strobes nBLE[1:0] are held LOW during any system reads or
RBLE
writes from memory.
RBLE is written 0 when interfacing to external 8-bit or non byte-partitioned
memory devices. When RBLE is 0, use nOE for read operations and nBLE[1:0]
for write operations (nWE is not used). When RBLE is 1, use nOE for read op-
erations and nBLE[1:0] and nWE and nBLE[1:0] for write operations.
Wait State1
For SRAM and ROM: WST1 is the read access time burst access time for
burst ROM.
WST1
For Burst ROM: WST1 is the initial access time. This wait state time is
(WST2) × tHCLK.
The wait state time is (WST1 + 1) × tHCLK. (Default = 11111)
///
Reserved Do not write. Do not modify. Unpredictable behavior when read.
Idle Cycle Memory Data Bus Turnaround Time The turnaround time is
IDCY
(IDCY + 1) × tHCLK. (Default = 1111)
LH75400/01/10/11 (Preliminary) User's Guide
DESCRIPTION
6/17/03
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