Clock And Signal Polarity Control Register; Table 14-11. Timing2 Register; Table 14-12. Timing2 Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

14.3.2.4 Clock and Signal Polarity Control Register

The Timing2 Register controls the LCDC timing.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:27
26
25:16
15
14
13
12
11
10:6
5
4:0

Table 14-11. Timing2 Register

31 30 29 28 27
///
0 0 0 0
R R R R
15 14 13 12 11
/// IOE IPC HIS IVS
0 0 0 0
R RW RW RW RW

Table 14-12. Timing2 Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Bypass Pixel Clock Divider
BCD 1 = Bypasses the pixel clock divider logic.
Always set to 0 for electroluminescent (EL) and STN displays.
Clocks Per Line Specifies the number of actual LCDDCLK clocks to the LCD panel on
CPL each line. This is the number of pixels per line divided by either 4 or 8, minus one. This must
be correctly programmed in addition to PPL for the LCD Controller to work correctly.
/// Reserved Writing to this bit has no effect. Reading returns 0.
Invert Output Enable Selects the active polarity of the output enable signal. In this mode,
the LCDEN pin is used as an enable that indicates to the LCD panel when valid display data
is available. In Active Display Mode, data is driven onto the LCD data lines at the pro-
IOE
grammed edge of LCDDCLK when LCDEN is in its active state.
0 = LCDEN output pin is active HIGH.
1 = LCDEN output pin is active LOW.
Invert Panel Clock Selects the edge of the panel clock on which pixel data is driven out
onto the LCD data lines.
IPC
0 = Data is driven on the LCDs data lines on the rising-edge of LCDDCLK.
1 = Data is driven on the LCDs data lines on the falling-edge of LCDDCLK.
Invert Horizontal Synchronization Inverts the polarity of the LCDLP signal.
HIS
0 = LCDLP pin is active HIGH and inactive LOW.
1 = LCDLP pin is active LOW and inactive HIGH.
Invert Vertical Synchronization Inverts the polarity of the CLFP signal.
IVS
0 = CLFP pin is active HIGH and inactive LOW.
1 = CLFP pin is active LOW and inactive HIGH.
AC Bias Pin Frequency The AC bias pin frequency is only applicable to STN displays,
which require the pixel voltage polarity to be periodically reversed to prevent damage due
ACB
to DC charge accumulation. Program this field with the required value minus one to apply
the number of line clocks between each toggle of the AC bias pin (LCDEN).
/// Reserved Writing to this bit has no effect. Reading returns 0.
Panel Clock Divisor Derives the LCD panel clock frequency LCDDCLK from the input
LCDC clock frequency, according to the formula LCDDCLK = LCDC CLOCK/(PCD + 2). For
PCD
monochrome STN displays with a 4- or 8-bit interface, the panel clock will be a factor of four
and eight down on the actual individual pixel clock rate.
26 25 24 23
BCD
0 0 0 0 0
R RW RW RW RW
10 9 8 7
ACB
0 0 0 0 0
RW RW RW RW
0xFFFF4000 + 0x08
DESCRIPTION
6/17/03
Liquid Crystal Display Controller
22 21 20 19 18
CPL
0 0 0 0 0
RW RW RW RW RW
6 5 4 3 2
/// PCD
0 0 0 0 0
RW R RW RW RW
17 16
0 0
RW RW
1 0
0 0
RW RW
14-11