Lcd Mode Muxing Register; Table 11-13. Lcd_Mux Register Definitions (Lh75401 And Lh75411 Soc Devices); Table 11-14. Lcd_Mux Register Definitions (Lh75400 And Lh75410 Soc Devices) - Sharp Blue Treak LH75400 User Manual

I/O Configuration

11.2.2.5 LCD Mode Muxing Register

LCD_MUX is the LCD Mode Muxing Register. This register allows the LCD display to be
configured to different modes supported by the SoC, freeing GPIO. The active bits used in
this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR

Table 11-13. LCD_MUX Register Definitions (LH75401 and LH75411 SoC Devices)

BIT
31:3
2:0

Table 11-14. LCD_MUX Register Definitions (LH75400 and LH75410 SoC Devices)

BIT
31:3
2:0
11-10
Table 11-12. LCD_MUX Register
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
R R R R R
NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
LCD Mode
000 = No LCD
001 = 4-bit Mono STN Mode
MODE
010 = 4-bit Mono STN Dual Mode
011 = 8-bit Mono/Color STN Mode
100 = TFT Mode
101 through 111 = No LCD
NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
LCD Mode
000 = No LCD
001 = 4-bit Mono STN Mode
MODE
010 = 4-bit Mono STN Dual Mode
011 = 8-bit Mono STN Mode
100 = Reserved
101 through 111 = No LCD
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0
R R R R R
10 9 8 7
///
0 0 0 0
R R R R R
0xFFFE5000 + 0x10
DESCRIPTION
DESCRIPTION
6/17/03
21 20 19 18
0 0 0 0 0
R R R R
6 5 4 3 2
0 0 0 0 0
R R R RW
17 16
0 0
R R
1 0
MODE
0 0
RW RW