Control Register; Table 22. Ctrl Register; Table 23. Ctrl Register Definitions - Sharp Blue Treak LH75400 User Manual

Real-Time Clock

17.3.2.8 Control Register

CTRL is a 1-bit Control Register that controls the masking of the interrupt generated by the
RTC. Writing a '1' to bit position 0 enables the interrupt. Writing a '0' disables the interrupt.
Reads to this register return the last value written at bit position 0.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT NAME
31:1
0
17.3.3 RTC Interrupts
The RTC generates a single maskable active HIGH interrupt, RTCINTR, when a match
occurs between the counter and the MR Registers. This interrupt is enabled or disabled by
changing the mask bit in the CTRL Register. To enable the interrupt, set bit [0] of the CTRL
Register to HIGH.
The status of the interrupt mask can be read via the CTRL Register. The RTCINTR status
can be read from bit [0] in the STAT Register. Writing to EOI clears the RTCINTR flag.
17-10
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 23. CTRL Register Definitions

/// Reserved Unpredictable behavior when read. Should be written as 0.
Match Interrupt Enable
MIE
0 = Match interrupt is not enabled.
1 = Match interrupt is enabled.
LH75400/01/10/11 (Preliminary) User's Guide

Table 22. CTRL Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
///
0 0 0 0
RW RW RW RW
0xFFFE0000 + 0x1C
FUNCTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
R R
1 0
MIE
0 0
RW RW