Transmit Machine Mode Register; Table 20-53. Tmd Register; Table 20-54. Tmd Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

20.3.2.22 Transmit Machine Mode Register

Register Bank: 2
TMD is the Transmit Machine Mode Register. The TMD Register, together with the LCR
Register, defines the transmitter operating mode.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7
6
5
4:3
2
1:0
31 30 29 28 27
0 0 0 0
R R R R
15 14 13 12 11
///
0 0 0 0
R R R R

Table 20-54. TMD Register Definitions

NAME
/// Reserved Do not modify. Read as zero.
Error Echo Disable
EED 1 = Disables echo of characters received with errors (valid in Echo Mode only).
Echo Mode select is set in the IMD Register.
Control Character Echo Disable
1 = Disables echo of characters recognized as control characters or
address characters in µLAN Mode (valid in Echo Mode only).
CED
The control character or address character is set in the ACR0 Register.
Echo Mode select is set in the IMD Register.
Nine-bit Length Works with bits [1:0] of the CLR Register to select
NBCL
transmit/receive character length of nine bits. See Table 20-23.
/// Reserved Read as zero.
Software Parity Force
1 = Defines the parity modes along with bits [5:3] of the LCR Register (see
Section 20.3.2.7). When software parity is enabled (see Table 20-21),
SPF
the software must determine the parity bit through the TxF Register on
transmission or check the parity bit in RxF upon reception. See
Table 20-23.
Stop Bit Length Works with bit [2] of the LCR Register to define the stop bit
SBL2, SBL1
length. For parity modes supported by the LCR Register, see Table 20-21.

Table 20-53. TMD Register

26 25 24 23
///
0 0 0 0 0
R R R R R
10 9 8 7
EED CED
0 0 0 0 0
R R R R RW
0xFFFC2000 + 0x0C
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
/// SPF
0 0 0 0 0
RW RW R R RW
UART2
17 16
0 0
R R
1 0
0 0
RW RW
20-33