Pins An7/Pj7 To An0/Pj0 - Sharp Blue Treak LH75400 User Manual

I/O Configuration

11.2.2.11 Pins AN7/PJ7 to AN0/PJ0

ADC_MUX is the Pins AN7/PJ7 to AN0/PJ0 Register. This register allows the secondary
function of the ADC interface pins to be configured as General Purpose Inputs. The active
bits used in this register are Read/Write.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
11-20
Table 11-25. ADC_MUX Register
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R
Table 11-26. ADC_MUX Register
BIT NAME
31:8 /// Reserved Writing to these bits has no effect. Reading returns 0.
Pin AN3/PJ7 Source
7 PJ7
0 = AN3 (LR/Y-)
1 = PJ7
Pin AN4/PJ6 Source
6 PJ6
0 = AN4 9Wiper)
1 = PJ6
Pin AN9/PJ5 Source
5 PJ5
0 = AN9
1 = PJ5
Pin AN2/PJ4 Source
4 PJ4
0 = AN2 (LL/Y+)
1 = PJ3
Pin AN8/PJ3 Source
3 PJ3
0 = AN8
1 = PJ3
Pin AN1/PJ2 Source
2 PJ2
0 = AN1 (UR/X-)
1 = PJ2
Pin AN6/PJ1 Source
1 PJ1
0 = AN6
1 = PJ1
Pin AN0/PJ0 Source
0 PJ0
0 = AN0 (UL/X+)
1 = PJ0
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
PJ7 PJ6
0 0 0 0 0
R R R RW RW
0xFFFE5000 + 0x28
DESCRIPTION
6/17/03
21 20 19 18 17
0 0 0 0 0
R R R R R
5 4 3 2 1
PJ5 PJ4 PJ3 PJ2 PJ1
0 0 0 0 0
RW RW RW RW RW
16
0
R
0
PJ0
0
RW