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Introduction
1.2 ARM and Thumb State
These SoCs consist of a 32-bit core processor with a 16-bit data bus that can operate in
ARM Thumb mode for executing 16-bit instructions. Thumb is an extension to the ARM
architecture. It contains 36 instruction formats drawn from the standard 32-bit ARM instruc-
tion set that have been re-coded into 16-bit-wide opcodes. On execution, the SoCs decom-
presses the 16-bit Thumb opcodes to its ARM instruction set equivalents, which are then
run normally.
Unlike processors that offer a mixed instruction set, these devices support Thumb-code
and ARM-code as two separate instruction sets. The fact that the two instruction sets are
separate means that decoding logic is extremely simple. This, in turn:
• Keeps silicon area small
• Maintains low power and MIPS/Watt performance
• Allows designers to keep their ARM 32-bit instruction set, while benefiting from the code-
size advantages of the Thumb instruction set.
The combination of the two instruction sets running on a single Thumb-aware core makes
these devices effective solutions to the code-size and performance problems of 16-bit sys-
tems. And since the thumb-aware core is simply an extension of the ARM architecture,
designers can:
• Compile for Thumb-code, ARM-code, or a mix of both
• Retain 32-bit RISC performance.
1.3 Bus Architecture
The SoCs employ the ARM Advanced Microcontroller Bus Architecture (AMBA) 2.0 inter-
nal bus protocol. Each device has three AHB masters on the AHB that control access to
the external memory and the on-chip peripherals:
• An ARM processor to fetch instructions and transfer data
• A DMA Controller to transfer between memory and UART0, UART1, an external periph-
eral, or memory
• An LCD Controller to refresh an LCD panel with data from the external memory or from
Tightly Coupled Memory if the frame buffer is 16 Kb or less.
The ARM7TDMI-S processor is the default bus master. Table 1-2 lists the priorities for the
three AHB masters. These levels are fixed and cannot change.
1-2
Table 1-2. Bus Master Priority
PRIORITY
CLCD Controller (LH75401 and LH75411)
1 (highest)
LCD Controller (LH75400 and LH75410)
2
DMA Controller
3 (lowest)
ARM7TDMI-S Core (default)
7/15/03
LH75400/01/10/11 (Preliminary) User's Guide
BUS MASTER PRIORITY
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