LH75400/01/10/11 (Preliminary) User's Guide
16.3.1.6 Counter Section 2 Register
CNT2 is the Counter Section 2 Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
16.3.1.7 Counter Section 3 Register
CNT3 is the Counter Section 3 Register.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
31
30
29
28
0
0
0
0
R
R
R
R
15
14
13
12
///
0
0
0
0
R
R
R
R
Table 16-13. CNT2 Register Definitions
NAME
///
Counter Sub-Section 2
31
30
29
28
0
0
0
0
R
R
R
R
15
14
13
12
///
0
0
0
0
R
R
R
R
Table 16-15. CNT3 Register Definitions
NAME
///
Counter Sub-Section 3
Table 16-12. CNT2 Register
27
26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
11
10
9
8
7
0
0
0
0
0
R
R
R
R
R
0xFFFE3000 + 0x14
Reserved Writing to these bits has no effect. Reading returns 0.
Current Count Value Holds bits [23:16] of the current
count value.
Table 16-14. CNT3 Register
27
26
25
24
23
///
0
0
0
0
0
R
R
R
R
R
11
10
9
8
7
0
0
0
0
0
R
R
R
R
R
0xFFFE3000 + 0x18
Reserved Writing to these bits has no effect. Reading returns 0.
Current Count Value Holds bits [31:24] of the current
count value.
6/17/03
Watchdog Timer
22
21
20
19
0
0
0
0
R
R
R
R
6
5
4
3
Counter Sub-Section 2
0
0
0
0
R
R
R
R
DESCRIPTION
22
21
20
19
0
0
0
0
R
R
R
R
6
5
4
3
Counter Sub-Section 3
0
0
0
0
R
R
R
R
DESCRIPTION
18
17
16
0
0
0
R
R
R
2
1
0
0
0
0
R
R
R
18
17
16
0
0
0
R
R
R
2
1
0
0
0
0
R
R
R
16-7