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LH75400/01/10/11 (Preliminary) User's Guide
21.1 GPIO Features ............................................................................................. 21-2
21.2 GPIO Theory of Operation ........................................................................... 21-2
20.3.1.2 Register Bank 1 .............................................................................. 20-8
20.3.1.3 Register Bank 2 .............................................................................. 20-8
20.3.1.4 Register Bank 3 .............................................................................. 20-9
20.3.2 UART2 Register Definitions ................................................................ 20-10
20.3.2.1 Transmit Buffered Data Register .................................................. 20-10
20.3.2.2 Receive Buffered Data Register ................................................... 20-11
20.3.2.3 BRGA Divisor Least Significant Byte Register ............................. 20-12
20.3.2.4 BRGA Divisor Most Significant Byte Register .............................. 20-13
20.3.2.5 General Enable Register .............................................................. 20-14
20.3.2.6 General Interrupt/Bank Register................................................... 20-15
20.3.2.7 Line Control Register.................................................................... 20-17
20.3.2.8 Loopback Control Register ........................................................... 20-19
20.3.2.9 Line Status Register ..................................................................... 20-20
20.3.2.10 Address/Control Character Register0 ........................................ 20-21
20.3.2.11 Transmit Character Flag Register .............................................. 20-22
20.3.2.12 Received Character Flags Register............................................ 20-23
20.3.2.13 Timer Control Register ............................................................... 20-24
20.3.2.14 Timer Status Register................................................................. 20-25
20.3.2.15 FIFO Level Register ................................................................... 20-26
20.3.2.16 Receive Command Register....................................................... 20-27
20.3.2.17 Receive Machine Status Register .............................................. 20-28
20.3.2.18 Transmit Command Register...................................................... 20-29
20.3.2.19 Internal Command Register........................................................ 20-30
20.3.2.20 General Status Register ............................................................. 20-31
20.3.2.21 FIFO Mode Register ................................................................... 20-32
20.3.2.22 Transmit Machine Mode Register............................................... 20-33
20.3.2.23 Internal Mode Register ............................................................... 20-34
20.3.2.24 Address/Control Character Register 1........................................ 20-35
20.3.2.25 Receive Interrupt Enable Register.............................................. 20-36
20.3.2.26 Receive Machine Mode Register................................................ 20-37
20.3.2.27 Clocks Configure Register.......................................................... 20-38
20.3.2.28 BRGA Configuration Register..................................................... 20-39
20.3.2.29 BRGB Divisor Least Significant Byte Register ........................... 20-40
20.3.2.30 BRGB Divisor Most Significant Byte Register ............................ 20-41
20.3.2.31 BRGB Configuration Register..................................................... 20-42
20.3.2.32 Timer Interrupt Enable Register ................................................. 20-43
20.3.3 UART2 Interrupts ................................................................................ 20-44
20.3.3.1 Acknowledge Modes .................................................................... 20-44
20.3.3.2 Interrupt Service ........................................................................... 20-45
21.2.1 GPIO Programmer's Model ................................................................... 21-3
21.2.2 GPIO Registers Summary ..................................................................... 21-3
21.2.3 GPIO Register Definitions ..................................................................... 21-4
21.2.3.1 Port A Data Register....................................................................... 21-4
21.2.3.2 Port B Data Register....................................................................... 21-5
6/17/03
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