Timers
15.2.2.16 Timer 2 Status Register
The Status Register bits are independent of the individual interrupt enables and are set to
1 upon all compare, capture, and overflow occurrences. To clear the status bits, write 1s
to the individual bits. This action clears the bit that was set in the register and clears the
corresponding interrupt, with the following exception. If the timer is stopped and the Timer
2 Compare Register (CMP0 or CMP1) value matches the Timer 2 Counter Register (CNT),
the corresponding status bit cannot be cleared until either the Timer 2 Compare Register
or the Timer 2 Counter Register value is changed.
Writing a 0 to any of the status bits does not affect the corresponding interrupt. Similarly,
writing a 1 to a bit that is not set does not affect the Status Register or interrupt.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
15-28
Table 15-34. Status Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
0
0
0
0
0
R
R
R
R
R
Table 15-35. Status Register Definitions
BITS FIELD NAME
31:5
///
4
CAP1_ST
3
CAP0_ST
2
CMP1_ST
1
CMP0_ST
0
OVF_ST
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
22
///
0
0
0
0
R
R
R
R
R
10
9
8
7
///
0
0
0
0
R
R
R
R
R
0xFFFC4000 + 0x58
DESCRIPTION
Reserved Read as zero.
Timer 2 Capture 1 Status To clear, write 1.
Timer 2 Capture 0 Status To clear, write 1.
Timer 2 Compare 1 Status To clear, write 1.
Timer 2 Compare 0 Status To clear, write 1.
Timer 2 Overflow Status To clear, write 1.
6/17/03
21
20
19
18
0
0
0
0
0
R
R
R
R
6
5
4
3
2
0
0
0
0
0
R
RW
RW
RW
17
16
0
0
R
R
1
0
0
0
RW
RW