Table 11-9. Pe_Mux Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide
BITS
31:10
9
8
7
6
5:4
3:2
5:2
1
0

Table 11-9. PE_MUX Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
PE7/SSPFRM Source
SSPFRM
0 = PE7
1 = SSPFRM
PE6/SSPCLK Source
SSPCLK
0 = PE6
1 = SSPCLK
PE5/SSPRX Source
SSPRX
0 = PE5
1 = SSPRX
PE4/SSPTX Source
SSPTX
0 = PE4
1 = SSPTX
Pin PE3/CANTX/UARTTX0 Source (LH75401 and LH75400 SoC only)
00 = PE3
CANTX
01 = CANTX1
10 = UARTTX0
11 = PE3
Pin PE2/CANRX/UARTRX0 Source (LH75401 and LH75400 SoC only)
00 = PE2
CANRX
01 = CANRX1
10 = UARTRX0
11 = PE2
/// Reserved Always write 0. (LH75410 and LH75411 SoC only)
PE1/UARTTX2 Source
UARTTX2
0 = PE1
1 = UARTTX2
PE0/UARTRX2 Source
UARTRX2
0 = PE0
1 = UARTRX2
DESCRIPTION
6/17/03
I/O Configuration
11-7