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Chapter 15
Timers
The timer block consists of three 16-bit timers:
• Timer 0 has five Capture Registers and two Compare Registers.
– Capture Registers: CAP0, CAP1, CAP2, CAP3, and CAP4
– Compare Registers: CMP0 and CMP1
• Timer 1 has two Capture Registers and two Compare Registers.
– Capture Registers: CAP0 and CAP1
– Compare Registers: CMP0 and CMP1
• Timer 2 has two Capture Registers and two Compare Registers.
– Capture Registers: CAP0 and CAP1
– Compare Registers: CMP0 and CMP1
The timers are clocked by the system clock, but have an internal scaled-down system
clock that is used for the PWM and compare functions.
All counters are incremented by an internal prescaled counter clock or external clock and
can generate an overflow interrupt when the counter goes from 0xFFFF to 0x0000. All
three timers have separate internal prescaled counter clocks, with either a common exter-
nal clock (CTCLK) or a prescaled version of the system clock.
The SoCs support nine Capture Registers. The Capture Registers have edge-selectable
inputs and can generate an interrupt, if desired.
The SoCs support six Compare Registers. The Compare Registers can force the compare
output pin either HIGH or LOW upon a match.
Each timer can generate a separate interrupt. The interrupt becomes active if any enabled
compare, capture, or overflow interrupt conditions occurs. The interrupt remains active
until all compare, capture, and overflow interrupts are cleared.
Figure 15-1 shows a block diagram that includes all three timers.
Figure 15-2 shows a block diagram of Timer 0.
Figure 15-3 shows a block diagram representing Timer 1 and Timer 2. These two timers
are identical.
6/17/03
15-1
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