Table 22-7. Sr Register Definitions - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary
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LH75400/01/10/11 (Preliminary) User's Guide
BITS NAME
31:8
7
6
5
4
3
2
1
0

Table 22-7. SR Register Definitions

///
Reserved Writing to these bits has no effect. Reading returns 0.
Bus Status
BS
0 = CAN Controller is involved in bus activities.
1 = CAN Controller is in the Bus Off state and not involved in bus activities.
Error Status
0 = Both error counters are below the warning limit.
ES
1 = At least one error counter has reached or exceeded the CPU warning limit
defined by the Error Warning Limit Register.
Transmit Status
TS
0 = No message is being transmitted.
1 = CAN Controller is in the process of transmitting a message.
Receive Status
RS
0 = Nothing is being received.
1 = CAN Controller is receiving a message.
Transmission Complete Status
TCS
0 = Last requested transmission has not completed.
1 = Last requested transmission has successfully completed.
Transmit Buffer Status
0 = Transmit buffer locked. The CPU cannot access the transmit buffer because
TBS
a message is either waiting for transmission or is being transmitted.
1 = Transmit buffer released. The CPU may write a message to the transmit buffer.
Data Overrun Status
0 = No data overrun has occurred since the last Clear Data Overrun command
was given.
DOS
1 = Data overrun. A message has been lost because there was not enough space
for that message in the receive FIFO. The overrun condition is only indicated
if the entire message was received. No overrun condition is shown if the mes-
sage did not complete — for example, as a result of an error.
Receive Buffer Status
0 = Receive buffer empty. No message currently available to be read.
RBS
1 = Receive buffer full. One or more complete messages are available to be read
from the receive FIFO via the receive buffer.
DESCRIPTION
6/17/03
Controller Area Network
22-11

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