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Chapter 16
Watchdog Timer
The Watchdog Timer (WDT) is a programmable timer that software has to reset at regular
intervals. Failing to reset the timer causes an interrupt to the system. Failing to service the
interrupt within the timeout period causes the WDT to set a flag that forces the RCPC to
generate a System Reset. At the WDT timeout, the RCPC sets the WDTO bit in the Reset
Status Register.
Figure 16-1 shows a block diagram of the WDT.
16.1 WDT Features
The WDT has the following features:
• The counter generates an interrupt at a set interval and the count reloads from the pre-
set value after reaching zero.
• The default timeout period is set to the minimum timeout of 2
• The WDT is driven by the APB.
• A built-in protection mechanism guards against interrupt-service failure.
• The WDT can be programmed to trigger a System Reset on a timeout.
• The WDT can be programmed to trigger an interrupt on the first timeout; then, if the ser-
vice routine fails to clear the interrupt, the next WDT timeout triggers a System Reset.
RESET, CLOCK
GENERATION AND
POWER CONTROL
(RCPC)
VECTORED
INTERRUPT
CONTROLLER
(VIC)
32
ADVANCED
HIGH-PERFORMANCE
BUS (AHB)
Figure 16-1. Watchdog Timer Block Diagram
6/17/03
WDT TIMEOUT RESET
PCLK
nWDINT
WATCHDOG TIMER
(WDT)
32
ADVANCED
PERIPHERAL
BUS (APB)
16
system clock cycles.
LH754xx-39
16-1
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