Lcd Panel Parameters, Lcd Panel Power, And Lcdc Control Register; Table 14-19. Ctrl Register; Table 14-20. Ctrl Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide
14.3.2.8 LCD Panel Parameters, LCD Panel Power, and
LCDC Control Register
CTRL is a Read/Write register that controls the LCDC operating mode.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:17
16
15
14
13:12
11
10:9

Table 14-19. CTRL Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
RW RW RW RW RW

Table 14-20. CTRL Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
LCD DMA FIFO Watermark Level
0 = HBUSREQM is raised when either of the two LCD DMA FIFOs
WATERMARK
have four or more empty locations.
1 = HBUSREQM is raised when either of the LCD DMA FIFOs have
eight or more empty locations.
LCD DMA FIFO Test Mode Enable
0 = LCD DMA FIFO inaccessible to user.
LDmaFIFOTME
1 = LCD DMA FIFO Read/Write access for FIFO RAM testing.
Set this bit only when LCD is disabled via bit [0] of this register.
/// Reserved Writing to this bit has no effect. Reading returns 0.
Generate Interrupt
00 = At start of vertical synchronization
LcdVComp
01 = At start of back porch
10 = At start of active video
11 = At start of front porch
LCD Power Enable This bit causes the LCDEN pin to toggle.
0 = LCD is OFF, LCDEN pin is LOW.
LcdPwr
1 = LCD is ON, LCDEN pin is HIGH if bit [0] of this register is HIGH.
When using this setting, set bit [0] to 1.
/// Reserved
Liquid Crystal Display Controller
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
/// ///
0 0 0 0 0
RW RW RW RW RW
0xFFFF4000 + 0x1C
DESCRIPTION
6/17/03
21 20 19 18 17
0 0 0 0 0
R R R R R
5 4 3 2 1
/// /// LcdBpp
0 1 0 0 0
R R RW RW RW
16
0
RW
0
0
RW
14-15