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LH75400/01/10/11 (Preliminary) User's Guide
20.3.3.2 Interrupt Service
A service operation is an operation that the CPU performs that resets the particular status
bit causing the UART2 interrupt. An interrupt request within UART 2 does not reset the sta-
tus bit until the interrupt source is serviced.
UART2 interrupt sources can be serviced in various ways. These include:
• Disabling the particular status bit. This method causes the interrupt to occur via the cor-
responding Block Enable Register.
• Setting the appropriate bit of the Enable Register to zero. This method masks off the corre-
sponding bit in the Status Register, causing an edge on the input line to the interrupt logic.
• Masking off the particular block interrupt request in General Status Register via the
General Enable Register. This method achieves the same effect as the Enable Register
method above.
Issuing the Status Clear command from the Internal Command Register. This method
is applicable to all sources. Table 20-75 lists the detailed service requirements for
each source.
INTERRUPT
SOURCE
Timers
(highest priority)
Transmitters
Receiver
Rx FIFO
Tx FIFO
(lowest priority)
Table 20-75. Interrupt Service Requirements
STATUS REGISTERS
(BIT NUMBER)
TMST (1-0)
GSR (5)
GSR (4)
LSR (4)
LSR (4-1)
RST (7-1)
GSR (2)
RST/LSR (0)
GSR (0)
LSR (5)
GSR (1)
6/17/03
MARK REGISTER
(BIT NUMBER)
TMIE (1-0)
Read TMST
GER (5)
GER (4)
Write Character to Tx FIFO
RIE (7-1)
Read RST or LSR Write 0 to
GER (2)
bit in RST/LSR
Write 0 to LSR/RST Bit zero
GER (0)
Read Character
Write to FIFO
GER (1)
Read GIR (1)
UART2
SPECIFIC SERVICE
20-45
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