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LH75400/01/10/11 (Preliminary) User's Guide
10.1.3 Vectored Interrupts
Each interrupt source line must be identified as either an IRQ type or an FIQ type using
the IntSelect Register (see Section 10.2.2.4). If the interrupt is designated as an FIQ type,
the FIQ interrupt service is non-vectored. Once the VIC causes the FIQ interrupt to be
asserted to the core, the FIQ interrupt handler is reached directly by loading the instruction
at 0x1C independently of the VIC.
If any default-vectored interrupts will be enabled, set the DefVectAddr Register to the entry
address of the ISR which is to handle all default-vectored interrupts (see
Section 10.2.2.10).
For each interrupt line that will be enabled as a vectored interrupt:
• Set the corresponding VectAddr(x) Register (where 'x' is 0-15) to the entry address of
the ISR which is to handle that specific interrupt.
• Set the IntSource field of the corresponding VectCtrl(x) Register to the interrupt source
for that specific vector. Then enable that interrupt source as a vectored interrupt using
the E field in that register.
Enable each interrupt line to be enabled, whether vectored or default-vectored, using the
IntEnable Register (see Section 10.2.2.5).
10.1.4 External Interrupts
All external interrupts are conditioned by the RCPC module before being presented to the
VIC. External interrupt conditioning can be configured to one of four triggers using the
RCPC IntConfig Register (see Chapter 9, Section 9.3.2.13):
• Low-level trigger
• High-level trigger
• Falling-edge trigger
• Rising-edge trigger.
On reset, all external interrupt triggers are LOW-level triggers. Exercise care to ensure that
all external interrupt input signals are HIGH at reset. External edge-triggered interrupts
must be cleared using the RCPC IntClear Register (see Section 9.3.2.14). If the external
interrupt is configured as a level-trigger interrupt, the external interrupt must be cleared,
reset, or disabled at its source (external to the SoC).
Table 10-1. Interrupt Assignments
POSITION
DESCRIPTION
26
UART1 UARTTXINTR
27
UART1 UARTINTR
28
UART0 UARTINTR
29
UART2 Interrupt
30
DMA
CAN
31
UART1
UART1
UART0
UART2
DMA
CAN (LH75401 and LH75400)
Reserved (LH75411 and LH75410)
6/17/03
Vectored Interrupt Controller
SOURCE
10-3
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