Baud Rate Generators - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary
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UART2

20.2.4 Baud Rate Generators

UART2 has two 16-bit baud-rate generators. These baud-rate generators are completely
independent of each other and can be separately configured as timers.
Dividing the system clock with the divisor count generates the baud rate. Either baud-rate
generator can clock either serial machine (transmitter or receiver). Alternatively, the two
baud-rate generators can be cascaded to provide a larger divisor that generates a single
baud rate for clocking both serial machines. The divisor for a single baud-rate generator
can operate with any divisor between 1 and 65,535.
Use the following formula to calculate the UART2 baud rate for a single-baud rate
generator:
ƒbaud
If two baud-rate generators are cascaded, use either of the following formulas to calculate
the single baud rate:
ƒbaud
or
ƒbaud
n these formulas:
I
• divisorA is defined by the BAH and BAL Registers.
• divisorB is defined by the BBH and BBL Registers.
• The divisor range for the cascaded baud-rate generators is 1 to 4,294,836,225.
When a baud-rate generator is configured as a timer, it counts down from its divisor/count
value (BAH/BAL or BBH/BBL) to 1 once it is enabled. A maskable Timer Expired interrupt
is generated upon terminal count. To start (or restart) counting, the software issues a Start
Timer command (see Section 20.3.2.13). The delay between the trigger and the terminal
count is determined by the following equation:
Delay = (count value) × (HCLK period)
The divisor (or count, depending on the mode) can be updated during operation, unless the
particular baud-rate generator is being used as a clock source by one of the serial machines
and the particular serial machine is operating at the time. Do not load the count registers
(BAL or BBL) with 0 at any time. Do not load the count registers with 1 in Timer Mode.
20-6
ƒHCLK
=
------------------------------- -
×
16
divisor
ƒHCLK
=
------------------------------------------------------------------
×
×
16
divisorA
divisorB
ƒHCLK
=
------------------------------------------------------------------
×
×
divisorA 16 divisorB
6/17/03
LH75400/01/10/11 (Preliminary) User's Guide

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