Timer 2 Control Register; Table 15-30. Ctrl Register; Table 15-31. Ctrl Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

15.2.2.14 Timer 2 Control Register

BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:15
14
13
12:11 CMP1
10:9

Table 15-30. CTRL Register

31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
/// PWM TC CMP1
0 0 0 0 0
R RW RW RW RW

Table 15-31. CTRL Register Definitions

FIELD
NAME
/// Reserved Read as zero.
PWM Output This bit allows the use of CTCMP2A as a PWM output. This is
done by properly setting up this bit as well as other bits in this register. Refer to
Section 15.1.1 for a complete explanation of this feature.
PWM
0 = Output CTCMP2A is normal and works only with the CMP2 Register.
1 = Output CTCMP2A is in PWM Mode.
Timer 2 Counter Operation This bit determines whether the counter is to oper-
ate as a free running counter or interval counter. When set, the counter clears
upon matching CMP1 for Timer 2. This operation is only available with the CMP1
Register for Timer 2. Refer to Section 15.1.1 for a complete explanation of this
TC
feature.
0 = Inhibit counter clear (operates as free running counter).
1 = Clear counter when CNT for Timer 2 matches CMP1 for Timer 2.
Output Value Select Sets the reference value (at which compare match
should occur) that is to be output to CTCMP2B when the CNT Register for Timer
2 matches the CMP1 Register for Timer 2.
00 = No change occurs to the output CTCMP2B.
01 = Output 0 to CTCMP2B.
10 = Output 1 to CTCMP2B.
11 = Toggle the output to CTCMP2B.
Output Value Select Sets the reference value (at which compare match
should occur) that is to be output to CTCMP2A when the CNT Register for
Timer 2 matches the CMP0 Register for Timer 2.
CMP0
00 = No change occurs to the output CTCMP2A.
01 = Output 0 to CTCMP2A.
10 = Output 1 to CTCMP2A.
11 = Toggle the output to CTCMP2A.
26 25 24 23 22
///
0 0 0 0 0
R R R R R
10 9 8 7 6
CMP0 CAP1
0 0 0 0 0
RW RW RW RW RW
0xFFFC4000 + 0x50
DESCRIPTION
6/17/03
21 20 19 18
0 0 0 0
R R R R
5 4 3 2
CAP0 SEL
0 0 0 0
RW RW RW RW
Timers
17 16
0 0
R R
1 0
CS CCL
0 0
RW RW
15-25