Interrupt Register; Table 22-8. Ir Register; Table 22-9. Ir Register Definitions - Sharp Blue Treak LH75400 User Manual

Controller Area Network

22.3.2.4 Interrupt Register

IR is the Interrupt Register. The IR Register allows the source of an interrupt to be identi-
fied. When one or more bits of this register are set, the CAN Controller sends an interrupt
to the CPU.
The IR Register appears to the CPU as Read Only memory. After the register has been
read by the CPU, all bits except Receive Interrupt are reset.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS NAME
31:8
7
6
5
4
3
2
1
0
22-12
31 30 29 28 27
0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0
R R R R R

Table 22-9. IR Register Definitions

/// Reserved Writing to these bits has no effect. Reading returns 0.
Bus Interrupt Error
BEI
1 = CAN Controller detects an error on the CAN bus, provided bit [7] of the Interrupt Enable
Register is set (see Section 22.3.2.5).
Arbitration Lost Interrupt
ALI
1 = CAN Controller loses arbitration and becomes a receiver, provided bit [6] of the Interrupt
Enable Register is set (see Section 22.3.2.5).
Error Passive Interrupt
1 = CAN Controller re-enters Error Active state after being in Error Passive state or when at
EPI
least one error counter exceeds the protocol-defined level of 127, provided bit [5] of the
Interrupt Enable Register is set (see Section 22.3.2.5).
Wake-Up Interrupt
1 = Bus activity is detected, provided bit [4] of the Interrupt Enable Register is set (see
WUI Section 22.3.2.5).
A wake-up interrupt is also generated if the CPU tries to set bit [4] of the MOD Register while
the CAN Controller is involved in bus activities or a CAN interrupt is pending.
Data Overrun Interrupt Set on a 0-to-1 transition of bit [1] of the CAN Status Register,
DOI
provided bit [3] of the Interrupt Enable Register is set (see Section 22.3.2.5).
Error Warning Interrupt Set on every change (set or clear) of either bit [7] or bit [6] of the
EI Status Register, provided bit [2] of the Interrupt Enable Register is set (see
Section 22.3.2.5).
Transmit Interrupt Set when bit [2] of the Status Register changes from 0 to 1 (released), pro-
TI
vided bit [1] of the Interrupt Enable Register is set (see Section 22.3.2.3 and Section 22.3.2.5).
Receive Interrupt Set when the receive buffer contains one or more messages, provided
bit [0] of the Interrupt Enable Register is set (see Section 22.3.2.5). Cleared when the Release
Receive Buffer command (bit [2] of the Command Register, described in Section 22.3.2.2) is
RI
issued, provided there is no further data to read in the receive buffer. The RI bit, when enabled,
mirrors bit [0] of the Status Register (described in Section 22.3.2.3). Consequently, it is not
cleared automatically when the Interrupt Register is read.
LH75400/01/10/11 (Preliminary) User's Guide

Table 22-8. IR Register

26 25 24 23
///
0 0 0 0 0
R R R R
10 9 8 7
BEI
0 0 0 0 0
R R R R
0xFFFC5000 + 0x0C
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
ALI EPI WUI DOI EI
0 0 0 0 0
R R R R R
17 16
0 0
R R
1 0
TI RI
0 0
R R