Lcdc Programmer's Model; Lcdc Register Summary; Table 14-6. Lcdc Register Summary - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

14.3 LCDC Programmer's Model

The base address for the LCDC is:
LDC Base Address: 0xFFFF4000
The following locations are reserved and must not be used during normal operation:
• Locations at offsets 0x030 through 0x1FC
• Locations at offsets 0x400 through 0x7FF.

14.3.1 LCDC Register Summary

NAME
Timing0
Timing1
Timing2
///
UPBASE
LPBASE
INTRENABLE
CTRL
Status
Interrupt
UPCURR
LPCURR
/// 0x030 - 0x1FC
Palette 0x200 - 0x3FC
/// 0x400 - 0x7FF

Table 14-6. LCDC Register Summary

ADDRESS RESET
TYPE
OFFSET VALUE
RW
0x000 0x00000000 Horizontal Timing Panel Control Register
0x004 0x00000000 Vertical Timing Panel Control Register
RW
0x008 0x0000000 Clock and Signal Polarity Control Register
RW
0x00C
RW
0x010 RW 0x0000000 Upper Panel Frame Buffer Base Address Register
0x014 0x00000000 Lower Panel Frame Buffer Base Address Register
RW
0x018 0x00000000 Interrupt Enable Register
RW
0x01C 0x0000
RW
0x020 RW 0x00000000 Raw Interrupt Status Register
0x024 R 0x00000000 Final Masked Interrupts Register
0x028 R 0x00000000 Upper Panel Frame Buffer Current Address Register
0x02C R 0x00000000 Lower Panel Frame Buffer Current Address Register
0x00000
RW
Liquid Crystal Display Controller
DESCRIPTION
Reserved
LCD Panel Parameters, LCD Panel Power, and
LCDC Control Register
Reserved
LCD Palette Register. Palette is addressed at 32 bits
Reserved
6/17/03 14-7