Controller Area Network
22.3.2.9 Error Code Capture Register
ECC is the Error Code Capture Register. The ECC Register contains information about the
type and location of errors on the bus.
When a bus error occurs:
• A Bus Error Interrupt is generated (if enabled) and the current bit position of the Bit
Processor is captured into this Error Code Capture Register.
• The contents of this register are maintained until the register has been read by user
software. Then the capture mechanism is activated again.
The Error Code Capture Register appears to the CPU as Read Only memory.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:8
7:6
5
4:0
Segment Code Segment Code Shows the segment code (see Table 22-22).
22-18
Table 22-19. ECC Register
31
30
29
28
27
0
0
0
0
0
R
R
R
R
R
15
14
13
12
11
///
0
0
0
0
0
R
R
R
R
R
Table 22-20. ECC Register Definitions
NAME
Reserved Writing to these bits has no effect. Reading returns 0.
///
Error Code
Error Code Shows the error code that occurred (see Table 22-21).
Error Direction
Direction
0 = Error occurred during transmission.
1 = Error occurred during reception.
ERROR CODE BITS [7:6]
LH75400/01/10/11 (Preliminary) User's Guide
26
25
24
23
///
0
0
0
0
R
R
R
R
10
9
8
7
Error Code
0
0
0
0
R
R
R
R
0xFFFC5000 + 0x30
DESCRIPTION
Table 22-21. Error Code
DESCRIPTION
Bit error
0 0
0 1
Form error
1 0
Stuff error
1 1
Other types of errors
6/17/03
22
21
20
19
18
0
0
0
0
0
R
R
R
R
R
6
5
4
3
2
Segment Code
0
0
0
0
0
R
R
17
16
0
0
R
R
1
0
0
0