Dmactrl; Table 19-31. Dmactrl Register Definitions - Sharp Blue Treak LH75400 User Manual

UART0 and UART1

19.3.1.16 DMACTRL

DMACTRL is the DMA Control Register. The active bits used in this register are Read/
Write. All the bits are cleared to '0' on System Reset.
BIT
15:3
2
1 TRANSMIT DMA ENABLE
0
19-24

Table 19-31. DMACTRL Register Definitions

NAME
///
DMA ON ERROR
RECEIVE DMA ENABLE
LH75400/01/10/11 (Preliminary) User's Guide
DESCRIPTION
Reserved Do not modify.
DMA on Error
1 = Disables the DMA receive request output,
UARTRXDMABREQ, when the UART Error Interrupt
is asserted.
Transmit DMA Enable
1 = Enables the DMA for the transmit FIFO.
Receive DMA Enable
1 = Enables the DMA for the receive FIFO.
7/15/03