Port E Data Direction Register; Table 21-23. Peddr Register; Table 21-24. Peddr Register Definitions - Sharp Blue Treak LH75400 User Manual

General Purpose Input/Output

21.2.3.11 Port E Data Direction Register

PEDDR is the Port E Data Direction Register. The active bits used in this register are
Read/Write. Bits set in PEDDR set the corresponding PE pin to be an output:
• Bit [7] controls pin 99 when the pin is configured as PE7. It does not control pin 99 when
the pin is configured as SSPFRM.
• Bit [6] controls pin 100 when the pin is configured as PE6. It does not control pin 100
when the pin is configured as SSPCLK.
• Bit [5] controls pin 101 when the pin is configured as PE5. It does not control pin 101
when the pin is configured as SSPRX.
• Bit [4] controls pin 102 when the pin is configured as PE4. It does not control pin 102
when the pin is configured as SSPTX.
• Bit [3] controls pin 103 when the pin is configured as PE3. It does not control pin 103
when the pin is configured as CANTX or UARTTX0.
• Bit [2] controls pin 104 when the pin is configured as PE2. It does not control pin 104
when the pin is configured as CANRX or UARTRX0.
• Bit [1] controls pin 105 when the pin is configured as PE1. It does not control pin 105
when the pin is configured as UARTTX2.
• Bit [0] controls pin 107 when the pin is configured as PE0. It does not control pin 106
when the pin is configured as UARTRX2.
Clearing a bit configures the pin to be an input. A System Reset clears all bits.
NOTE: The CANTX and CANRX functions apply to the LH75400 and LH75401 SoC devices only.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
21-14

Table 21-23. PEDDR Register

31 30 29 28 27
0 0 0 0
R R R R
15 14 13 12 11
///
0 0 0 0
R R R R

Table 21-24. PEDDR Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Port E Output/Input
Port E Data Direction
Bits set = Port E output.
Bits cleared = Port E input.
LH75400/01/10/11 (Preliminary) User's Guide
26 25 24 23
///
0 0 0 0 0
R R R R R
10 9 8 7
0 0 0 0 0
R R R R RW
0xFFFDD000 + 0x08
6/17/03
22 21 20 19
0 0 0 0
R R R R
6 5 4 3
Port E Data Direction
0 0 0 0
RW RW RW RW
FUNCTION
18 17 16
0 0 0
R R R
2 1 0
0 0 0
RW RW RW