Clcdc Register Definitions; Horizontal Timing Panel Control Register; Table 13-10. Timing0 Register; Table 13-11. Timing0 Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

13.3.2 CLCDC Register Definitions

13.3.2.1 Horizontal Timing Panel Control Register

The Timing0 Register controls:
• Horizontal Synchronization Pulse Width (HSW)
• Horizontal Front Porch (HFP) period
• Horizontal Back Porch (HBP) period
• Pixels-Per-Line (PPL)
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:24
23:16
15:8
7:2
1:0

Table 13-10. Timing0 Register

31 30 29 28 27
HBP
0 0 0 0 0
RW RW RW RW RW
15 14 13 12 11
HSW
0 0 0 0 0
RW RW RW RW RW

Table 13-11. Timing0 Register Definitions

NAME
Horizontal Back Porch Specifies the number of LCDDCLK periods between
the falling edge of LCDLP and the start of active data; that is, the number of pixel
clock periods inserted at the beginning of each line or row of pixels. Program
HBP
with value minus 1. After the line clock for the previous line has been de-assert-
ed, the value in HBP counts the number of pixel clocks to wait before starting the
next display line. HBP can generate a delay of 1 to 256 pixel clock cycles.
Horizontal Front Porch Specifies the number of LCDDCLK periods between
the end of active data and the rising edge of LCDLP; that is, the number of pixel
clock intervals at the end of each line or row of pixels before the LCD line clock
HFP is pulsed. Program with value minus 1. Once a complete line of pixels is trans-
mitted to the LCD driver, the value in HFP counts the number of pixel clocks to
wait before asserting the line clock. HFP can generate a period of 1 to 256 pixel
clock cycles.
Horizontal Synchronization Pulse Width Specifies the width of the LCDLP
signal in LCDDCLK periods; that is, the pulse width of the line clock in Passive
HSW
Mode or the horizontal synchronization pulse in Active Mode. Program with
value minus 1.
Pixels-Per-Line Specifies the number of pixels, between 16 and 1,024, in
PPL each line or row of the screen. PPL counts the number of pixel clocks that occur
before the HFP is applied (program the value required divided by 16, minus 1).
/// Reserved Writing to these bits has no effect. Reading returns 0.
Color Liquid Crystal Display Controller
26 25 24 23 22
0 0 0 0 0
RW RW RW RW RW
10 9 8 7 6
0 0 0 0 0
RW RW RW RW RW
0xFFFF4000 + 0x00
DESCRIPTION
7/15/03
21 20 19 18 17
HFP
0 0 0 0 0
RW RW RW RW RW
5 4 3 2 1
PPL
0 0 0 0 0
RW RW RW RW R
16
0
RW
0
///
0
R
13-11