Interrupt, Error, And Status Registers; Dma Controller Timing Diagrams - Sharp Blue Treak LH75400 User Manual

Direct Memory Access Controller

12.2.1 Interrupt, Error, and Status Registers

The SoCs provide Interrupt, Error, and Status Registers for controlling the generation of
an interrupt, error-handling control, and active-stream monitoring. Each stream has its own
interrupt flag, which is set after the last transfer completes. Each of the four interrupt flags
can be masked and cleared independently.
Each stream also has its own error flag. An error flag is set when the data stream transfer
is aborted due to an ERROR response from an AHB slave. Each of the four error flags can
be separately masked and cleared. The masked interrupt and error flags are all combined
into a single interrupt output.

12.2.2 DMA Controller Timing Diagrams

Figure 12-1 and Figure 12-2 show examples of DMA timing diagrams.
• Figure 12-1 shows the timing for a peripheral-to-memory data transfer, where
SoSize = DeSize and SoBurst = 4.
• Figure 12-2 shows the timing for a memory-to-peripheral data transfer, where
SoSize = DeSize and SoBurst = 4.
12-4
LH75400/01/10/11 (Preliminary) User's Guide
7/15/03