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Static Memory Controller
7.2.4 External Memory Bus Cycle
As previously mentioned, the external memory bus cycle commences with the assertion of
nCS(x) and ends when it is de-asserted. In addition to a programmable number of wait
states for a read or write, the SoC supports a programmable number of wait states (from
1 to 32) for enabling the external bus to 'turn around' from a read to a write. This value can
be programmed from 1 and 32. Table 7-2 lists the turnaround cycles for which the register
values can be used.
Read from a memory bank, then write to the same memory bank
Read from a memory bank, then write to a different memory bank
Write to a memory bank, then write to the same memory bank
Write to a memory bank, then write to a different memory bank
Write to a memory bank, then read from the same memory bank
Write to a memory bank, then read from a different memory bank
NOTE: All SMC operations assume a Little Endian memory operation.
The Byte Lane Enable signals are used to control instances when:
• Data transfers are smaller than the width of the memory devices being used.
• Memory is configured to be wider than the memory devices that it is made from.
The Byte Lane Enable signals can be programmed to be either all active or all inactive dur-
ing reads. The SMC performs the mapping to ensure that each byte read is at the correct
location in the system bus. During writes, the nBLE[1:0] signals:
• Ensure that only the external device in a memory bank for which the data is intended will
perform the write
• Direct the device to 'steer' the data to the correct portion of its memory, if the external
device is wider than the data.
As this shows, the SMC considers many factors when generating the nBLE[1:0] signals.
These include:
• AMBA transfer width
• External memory bank data bus width
• External memory bank type, being byte, halfword, or word
• The decoded HADDR[2:0] value for write accesses only.
7-8
Table 7-2. SMC Bus Turnaround Usage
EXTERNAL BUS TRANSFER
6/17/03
LH75400/01/10/11 (Preliminary) User's Guide
TURNAROUND CYCLE
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