Iocon Register Definitions; Ebi Interface Muxing Register; Table 11-2. Ebi_Mux Register (16-Bit Mode); Table 11-3. Ebi_Mux Register (8-Bit Mode) - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

11.2.2 IOCON Register Definitions

Multi-bit pin configuration fields may have a bit setting called 'Reset Condition'. Setting the
bit field to this configures the pin to be the same as it would be set after a System Reset.

11.2.2.1 EBI Interface Muxing Register

EBI_MUX is the EBI Interface Muxing Register. This register allows the secondary function
of the EBI interface pins to be configured as GPIO. The active bits used in this register are
Read/Write.
NOTE: The register's reset value is based on whether the system is booted in 16-bit or 8-bit Mode. In 16-bit
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
Mode, the reset value is 0x4000. In 8-bit Mode, the reset value is 0x0000.

Table 11-2. EBI_MUX Register (16-bit Mode)

31 30 29 28
0 0 0 0
R R R R
15 14 13 12
///
0 1 0 0
R RW RW RW RW

Table 11-3. EBI_MUX Register (8-bit Mode)

31 30 29 28
0 0 0 0
R R R R
15 14 13 12
///
0 0 0 0
R RW RW RW RW
27 26 25 24 23
///
0 0 0 0 0
R R R R R
11 10 9 8 7
A23
0 0 0 0 0
RW RW RW RW
0xFFFE5000 + 0x00
27 26 25 24 23
///
0 0 0 0 0
R R R R R
11 10 9 8 7
A23
0 0 0 0 0
RW RW RW RW
0xFFFE5000 + 0x00
6/17/03
I/O Configuration
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
A22 A21 A20 A19 A18
0 0 0 0 0
RW RW RW RW RW
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
A22 A21 A20 A19 A18
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
R R
1 0
A17
A16
0 0
RW RW
17 16
0 0
R R
1 0
A17
A16
0 0
RW RW
11-3