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LH75400/01/10/11 (Preliminary) User's Guide
Table 10-9. IntSelect Register................................................................................ 10-12
Table 10-10. IntSelect Register Definitions ............................................................ 10-12
Table 10-11. IntEnable Register............................................................................. 10-13
Table 10-12. IntEnable Register Definitions........................................................... 10-13
Table 10-13. IntEnClear Register........................................................................... 10-14
Table 10-14. IntEnClear Register Definitions ......................................................... 10-14
Table 10-15. SoftInt Register ................................................................................. 10-15
Table 10-16. SoftInt Register Definitions................................................................ 10-15
Table 10-17. SoftIntClear Register......................................................................... 10-16
Table 10-18. SoftIntClear ....................................................................................... 10-16
Table 10-19. VectAddr Register ............................................................................. 10-17
Table 10-20. VectAddr Register Definitions ........................................................... 10-17
Table 10-21. DefVectAddr Register ....................................................................... 10-18
Table 10-22. DefVectAddr Register Definitions...................................................... 10-18
Table 10-23. VectAddr Registers ........................................................................... 10-19
Table 10-24. VectAddr Register Definitions ........................................................... 10-19
Table 10-25. VectCtrl Registers ............................................................................. 10-20
Table 10-26. VectCtrl Register Definitions ............................................................. 10-20
Chapter 11 - I/O Configuration
Table 11-1. IOCON Register Summary.................................................................... 11-2
Table 11-2. EBI_MUX Register (16-bit Mode).......................................................... 11-3
Table 11-3. EBI_MUX Register (8-bit Mode)............................................................ 11-3
Table 11-4. EBI_MUX Register Definitions .............................................................. 11-4
Table 11-5. PD_MUX Register................................................................................. 11-5
Table 11-6. PD_MUX Register Definitions ............................................................... 11-5
Table 11-7. PE_MUX Register (LH75401 and LH75400) ........................................ 11-6
Table 11-8. PE_MUX Register (LH75410 and LH75411) ........................................ 11-6
Table 11-9. PE_MUX Register Definitions ............................................................... 11-7
Table 11-10. TIMER_MUX Register......................................................................... 11-8
Table 11-11. TIMER_MUX Register Definitions....................................................... 11-8
Table 11-12. LCD_MUX Register........................................................................... 11-10
(LH75401 and LH75411 SoC Devices) .............................................................. 11-10
(LH75400 and LH75410 SoC Devices) .............................................................. 11-10
Table 11-15. PA_RES_MUX Register.................................................................... 11-11
Table 11-16. PA_RES_MUX Register Definitions.................................................. 11-11
Table 11-17. PB_RES_MUX Register.................................................................... 11-13
Table 11-18. PB_RES_MUX Register Definitions.................................................. 11-13
Table 11-19. PC_RES_MUX Register ................................................................... 11-14
Table 11-20. PC_RES_MUX Register Definitions.................................................. 11-14
Table 11-21. PD_RES_MUX Register ................................................................... 11-16
Table 11-22. PD_RES_MUX Register Definitions.................................................. 11-16
Table 11-23. PERES_MUX Register...................................................................... 11-18
Table 11-24. PE_RES_MUX Register Definitions.................................................. 11-18
Table 11-25. ADC_MUX Register .......................................................................... 11-20
Table 11-26. ADC_MUX Register .......................................................................... 11-20
6/17/03
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