Internal Command Register; Table 20-47. Icm Register; Table 20-48. Icm Register Definitions - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary

Table of Contents

20.3.2.19 Internal Command Register

ICM is the Internal Command Register. The active bits used in this register are Write Only.

NOTE: The reset value of this register's bits is indeterminate.

Reserved Do not modify. Read as zero.

Interrupt Acknowledge This bit provides for an explicit acknowledgement of

the device interrupt request. This bit is provided for Manual Acknowledge Mode

(see Section 20.3.3.1).

This bit forces the INT pin inactive for two clock cycles. After two clock cycles have

elapsed, the INT pin can go active again if other enabled interrupts are pending.

Status Clear

1 = Clears the RST, MSR, and TMST Registers.

Reserved Read as zero.

LH75400/01/10/11 (Preliminary) User's Guide

0xFFFC2000 + 0x1C