Brga Divisor Least Significant Byte Register; Table 20-9. Bal Register; Table 20-10. Bal Register Definitions - Sharp Blue Treak LH75400 User Manual

UART2

20.3.2.3 BRGA Divisor Least Significant Byte Register

Register Bank: 0
BAL is the BRGA Divisor Least Significant Byte Register. The BAL Register holds the least-
significant byte of the BRGA divisor/count value. The Divisor Latch Access Bit (DLAB) bit in
the LCR Register must be set to access this register (see Section 20.3.2.7). The possible
programmed values for this register range from 2 to 65,535.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:8
7:0
20-12
31 30 29 28 27
0 0 0 0 0
R R R R R
15 14 13 12 11
///
0 0 0 0 0
R R R R R

Table 20-10. BAL Register Definitions

NAME
/// Reserved Do not modify. Read as zero.
Least-Significant Byte of BRGA Divisor/Count Value Bit [7] holds
D7:D0
the most-significant bit. Bit [0] holds the least-significant bit.
LH75400/01/10/11 (Preliminary) User's Guide

Table 20-9. BAL Register

26 25 24 23
///
0 0 0 0
R R R R
10 9 8 7
D7
0 0 0 0
R R R RW
0xFFFC2000 + 0x00
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
D6 D5 D4 D3 D2
0 0 0 0 0
RW RW RW RW RW
17 16
0 0
R R
1 0
D1 D0
1 0
RW RW