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19.1 UART0 and UART1 Features....................................................................... 19-2
19.2 UART0 and UART1 Theory of Operation..................................................... 19-2
19.3 UART0 and UART1 Programmer's Model ................................................... 19-5
20.1 UART2 Features .......................................................................................... 20-2
20.2 UART2 Theory of Operation......................................................................... 20-2
20.3 UART2 Programmer's Model ....................................................................... 20-7
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18.5.3 SSP Interrupts ..................................................................................... 18-19
18.5.3.1 Receive Interrupt .......................................................................... 18-19
18.5.3.2 Transmit Interrupt ......................................................................... 18-19
18.5.3.3 Receive Overrun Interrupt ............................................................ 18-19
18.5.3.4 Receive Timeout Interrupt ............................................................ 18-20
18.5.3.5 SSPINTR ...................................................................................... 18-20
19.2.1 UART0 and UART1 Receiver Data Frame............................................ 19-2
19.2.2 Status Conditions .................................................................................. 19-3
19.2.3 On-Chip DMA Capabilities .................................................................... 19-4
19.2.4 Programming Control Registers ............................................................ 19-4
19.3.0.1 UART0 and UART1 Register Summary ........................................ 19-5
19.3.1 UART0 and UART1 Register Definitions............................................... 19-6
19.3.1.1 Data Register.................................................................................. 19-6
19.3.1.2 Receive Status/Error Clear Register.............................................. 19-8
19.3.1.3 Flag Register ................................................................................ 19-10
19.3.1.4 UART Line Control Register ......................................................... 19-11
19.3.1.5 Integer Baud Rate Divisor Register .............................................. 19-12
19.3.1.6 Fractional Baud Rate Divisor Register ......................................... 19-13
19.3.1.7 Calculating the Divisor Value........................................................ 19-14
19.3.1.8 Typical Bit Rates and Their Corresponding Divisor...................... 19-14
19.3.1.9 Line Control Register.................................................................... 19-15
19.3.1.10 UART Control Register............................................................... 19-17
19.3.1.11 Interrupt FIFO Level Select Register .......................................... 19-18
19.3.1.12 Interrupt Mask Set/Clear Register .............................................. 19-19
19.3.1.13 Raw Interrupt Status Register .................................................... 19-21
19.3.1.14 Masked Interrupt Status Register ............................................... 19-22
19.3.1.15 ICR ............................................................................................. 19-23
19.3.1.16 DMACTRL .................................................................................. 19-24
19.3.2 UART0 and UART1 Interrupts............................................................. 19-25
19.3.2.1 UARTRXINTR .............................................................................. 19-25
19.3.2.2 UARTTXINTR............................................................................... 19-25
19.3.2.3 UARTINTR ................................................................................... 19-25
20.2.1 UART Receiver Data Frame ................................................................. 20-3
20.2.2 Status Conditions .................................................................................. 20-5
20.2.3 Disabling the Loading of Incoming Characters...................................... 20-5
20.2.4 Baud Rate Generators .......................................................................... 20-6
20.3.1 UART2 Register Summary .................................................................... 20-7
20.3.1.1 Register Bank 0 .............................................................................. 20-7
LH75400/01/10/11 (Preliminary) User's Guide
6/17/03
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