Table of Contents
Advertisement
Color Liquid Crystal Display Controller
13.2.4 Palette RAM
The CLCDC includes a 256 × 16 bit dual-port RAM-based palette. The least-significant bit
of the serialized pixel data selects the upper or lower half of the palette RAM, based on the
Byte Ordering Mode.
• One port of the dual-port palette RAM is used as a Read/Write port and is connected to
the AHB slave interface. Palette entries can be written and verified through this port.
• The second port of the dual-port palette RAM is used as a Read Only port and is
connected to the unpacker and grayscaler.
Table 13-4 shows the bit representations of each word in the palette for TFT and
STN displays.
13-6
Table 13-4. Palette Data Storage
BIT (TFT)
BIT (STN)
31:30
31
29:26
30:27
25
26
24:21
25:22
20
21
19:16
20:17
15:14
16:15
13:10
14:11
9
10
8:5
9:6
4
5
3:0
4:1
—
0
NOTE: Blue and red palette data can swap places, depending on the setting
of bit [8] of the LCD Control Register (see Section 13.3.2.8).
7/15/03
LH75400/01/10/11 (Preliminary) User's Guide
NAME
DESCRIPTION
///
Unused.
B[3:0]
Blue palette data
///
Unused.
G[3:0]
Green palette data
///
Unused.
R[3:0]
Red palette data
///
Unused.
B[3:0]
Blue palette data
///
Unused.
G[3:0]
Green palette data
///
Unused.
R[3:0]
Red palette data
///
Unused.
Advertisement
Table of Contents
