Table of Contents
Advertisement
LH75400/01/10/11 (Preliminary) User's Guide
15.1 Timer Theory of Operation
15.1.1 Count Timing
Each counter can use either one of the supported internal divided-by-n system clocks or
an external clock as its count clock. Selection between one of the internal system clocks
or the external clock is accomplished using the Timer Control Register that corresponds to
the timer that is to be programmed.
The count clock to be applied to the counter can be changed only when the counter is in
Stop Mode. If you try to change the count clock while the counter is running, the new count
clock is ignored.
To change the count clock:
1.
Stop the counter by writing a 0 to the CS bit of the appropriate Timer Control Register.
2.
Select a desired clock by writing a value to the SEL bits of the same Timer Control
Register accessed in step 1.
3.
Start the counter by writing a 1 to the CS bit of the same Timer Control Register
accessed in the previous steps.
If you select CTCLK in step 2, the timer increments the counter of the corresponding Timer
Control Register on the third rising edge of system clock after a rising edge by CTCLK. The
pulse length of CTCLK must be equal to or longer than two system clock periods, plus the
setup and hold time. Shorter pulses can cause wrong counts. If CTCLK is not in phase with
the system clock, inaccurate counts can occur.
Figure 15-4 shows the timing of CTCLK with respect to system clock when the two are in
phase. Figure 15-5 shows the timing of CTCLK with respect to system clock when the two
are not in phase.
SYSTEM
CLOCK
CTCLK
COUNTER
VALUE
Figure 15-4. Count Clock Timing (System Clock in Phase with CTCLK)
SYSTEM
CLOCK
CTCLK
COUNTER
VALUE
Figure 15-5. Count Clock Timing (System Clock not in Phase with CTCLK)
N
N
6/17/03
N+1
N+1
Timers
N+2
LH754xx-19
N+2
LH754xx-20
15-5
Advertisement
Table of Contents
