Interrupt Enable Register; Table 10-11. Intenable Register; Table 10-12. Intenable Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

10.2.2.5 Interrupt Enable Register

IntEnable is the Interrupt Enable Register. This register enables the interrupt request lines,
by masking the interrupt sources for the IRQ interrupt.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BIT
31:0 IntEnable

Table 10-11. IntEnable Register

31 30 29 28 27
0 0 0 0 0
RW RW RW RW RW
15 14 13 12 11
0 0 0 0 0
RW RW RW RW RW

Table 10-12. IntEnable Register Definitions

NAME
Interrupt Enable Corresponds to the interrupt order in the Interrupt Assign-
ments table (see Table 10-1). When any bit position is read:
0 = Interrupt is disabled.
1 = Interrupt is enabled, allowing interrupt request to ARM7TDMI-S core.
When any bit position is written to:
0 = Has no effect.
1 = Enable the corresponding interrupt.
On System Reset, all interrupts are disabled.
26 25 24 23 22
IntEnable
0 0 0 0 0
RW RW RW RW RW
10 9 8 7 6
IntEnable
0 0 0 0 0
RW RW RW RW RW
0x010
0xFFFFF000 +
DESCRIPTION
6/17/03
Vectored Interrupt Controller
21 20 19 18
0 0 0 0
RW RW RW RW RW
5 4 3 2
0 0 0 0
RW RW RW RW RW
17 16
0 0
RW
1 0
0 0
RW
10-13