Fifo Mode Register; Table 20-51. Fmd Register; Table 20-52. Fmd Register Definitions - Sharp Blue Treak LH75400 User Manual

UART2

20.3.2.21 FIFO Mode Register

Register Bank: 2
FMD is the FIFO Mode Register. The FMD Register configures the Tx and Rx FIFOs thresh-
old levels; the number of characters contained in the FIFOs that can cause an interrupt.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:6
5:4
3:2
1:0
20-32
31 30 29 28 27
0 0 0 0
R R R R
15 14 13 12 11
0 0 0 0
R R R R

Table 20-52. FMD Register Definitions

NAME
/// Reserved Do not modify. Read as zero.
Receive FIFO Threshold When the number of characters in the Rx FIFO
RFT1, RFT0 is greater than the number indicated by these bits, the Rx FIFO interrupt
is activated.
/// Reserved Read as zero.
Transmit FIFO Threshold When the number of characters in the Tx
TFT1, TFT0 FIFO is less than or equal to the number indicated by these bits, the Tx
FIFO interrupt is activated.
LH75400/01/10/11 (Preliminary) User's Guide

Table 20-51. FMD Register

26 25 24 23
///
0 0 0 0 0
R R R R R
10 9 8 7
///
0 0 0 0 0
R R R R R
0xFFFC2000 + 0x04
DESCRIPTION
6/17/03
22 21 20 19 18
0 0 0 0 0
R R R R R
6 5 4 3 2
RFT1 RFT0 ///
0 0 0 0 0
R RW RW R R
17 16
0 0
R R
1 0
TFT1 TFT0
0 0
RW RW