Bus Timing Register 1; Figure 22-2. General Structure Of A Bit Period; Table 22-14. Btr1 Register; Table 22-15. Btr1 Register Definitions - Sharp Blue Treak LH75400 User Manual

System-on-chip preliminary

Table of Contents

LH75400/01/10/11 (Preliminary) User's Guide

22.3.2.7 Bus Timing Register 1

BTR1 is one of two CAN timing registers (BTR0 is the other). Together, these two registers

define the structure of the bit period.

The BTR1 Register defines the length of the bit period, the location of the sample point and

the number of samples to be taken at each sample point. This register can only be written

to in Reset Mode. In Operating Mode, it is Read Only.

Reserved Writing to these bits has no effect. Reading returns 0.

0 = Bus will be sampled once. This is recommended for high-speed bus-

es (SAE class C).

1 = Bus will be sampled three times. This is recommended for low- and

medium-speed buses (class A or B).

TSEG1 and TSEG2 Determines the number of CAN clock cycles (time

quanta) per bit period and the location of the sample point, as given by

the parameters tSYNCSEG, tTSEG1, and tTSEG2 in Figure 22-2. Pro-

gram this value according to the number of CAN clock cycles minus 1.

For example, if the number of CAN clock cycles for TSEG1 is 6, program

TSEG1 with a value of 5.

0xFFFC5000 + 0x1C

SAMPLE POINT(s)

Controller Area Network