Port F Data Direction Register; Table 21-25. Pfddr Register; Table 21-26. Pfddr Register Definitions - Sharp Blue Treak LH75400 User Manual

LH75400/01/10/11 (Preliminary) User's Guide

21.2.3.12 Port F Data Direction Register

PFDDR is the Port F Data Direction Register. The active bits used in this register are
Read/Write.
Bits set in PFDDR set the corresponding PF pin to be an output:
• Bit [6] controls pin 108 when the pin is configured as PF6. it does not control pin 108
when the pin is configured as CTCAP2B or CTCMP2B.
• Bit [5] controls pin 109 when the pin is configured as PF5. It does not control pin 109
when the pin is configured as CTCAP2A or CTCMP2A.
• Bit [4] controls pin 110 when the pin is configured as PF4. It does not control pin 110
when the pin is configured as CTCAP1B or CTCMP1B.
• Bit [3] controls pin 111 when the pin is configured as PF3. It does not control pin 111
when the pin is configured as CTCAP1A or CTCMP1A.
• Bit [2] controls pin 113 when the pin is configured as PF2. It does not control pin 113
when the pin is configured as CTCAP0E.
• Bit [1] controls pin 114 when the pin is configured as PF1. It does not control pin 114
when the pin is configured as CTCAP0D.
• Bit [0] controls pin 115 when the pin is configured as PF0. it does not control pin 115
when the pin is configured as CTCAP0C.
Clearing a bit configures the pin to be an input. A System Reset clears all bits.
BIT
FIELD
RESET
RW
BIT
FIELD
RESET
RW
ADDR
BITS
31:7
6:0

Table 21-25. PFDDR Register

31 30 29 28 27
0 0 0 0
R R R R
15 14 13 12 11
0 0 0 0
R R R R

Table 21-26. PFDDR Register Definitions

NAME
/// Reserved Writing to these bits has no effect. Reading returns 0.
Port F Output/Input
Port F Data Direction
Bits set = Port F output.
Bits cleared = Port F input.
26 25 24 23
///
0 0 0 0 0
R R R R R
10 9 8 7
///
0 0 0 0 0
R R R R R
0xFFFDD000 + 0x0C
6/17/03
General Purpose Input/Output
22 21 20 19
0 0 0 0
R R R R
6 5 4 3
Port F Data Direction
0 0 0 0
RW RW RW RW
FUNCTION
18 17 16
0 0 0
R R R
2 1 0
0 0 0
RW RW RW
21-15